? 1994 fairchild semiconductor corporation www.fairchildsemi.com february 2009 74lvxc3245 ? 8-bit dual supply configurable volt age interface transceiver with 3-state outputs 74lvxc3245 8-bit dual supply configurable voltage interface transceiver with 3-state outputs features bidirectional interface between 3v and 3v-to-5v buses control inputs compatible with ttl level outputs source/sink up to 24 ma guaranteed simultaneous switching noise level and dynamic threshold performance implements patented emi reduction circuitry flexible v ccb operating range allows b port and v ccb to float simultaneously when oe is high functionally compatible with the 74 series 245 general description the lvxc3245 is a 24-pin dual-supply, 8-bit configurable voltage interface transceiver suited for pcmcia and other real time configurable i/o applications. the v cca pin accepts a 3v supply level. the a port is a dedicated 3v port. the v ccb pin accepts a 3v-to-5v supply level. the b port is configured to track the v ccb supply level respec- tively. a 5v level on the v cc pin will configure the i/o pins at a 5v level and a 3v v cc will configure the i/o pins at a 3v level. the a port should interface with a 3v host system and the b port to the card slots. this device will allow the v ccb voltage source pin and i/o pins on the b port to float when oe is high. this feature is necessary to buffer data to and from a pcmcia socket that permits pcmcia cards to be inserted and removed during normal operation. ordering code: devices also available in tape and reel. specify by appending suffix letter ?x? to the ordering code. logic symbol/s pin descriptions connection diagram/s order number package number package description 74lvxc3245wm m24b 224-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74lvxc3245qsc mqa24 24-lead quarter size outline package (qsop), jedec mo-137, 0.150" wide 74lvxc3245mtc mtc24 24-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pin names description oe output enable input t/r transmit/receive input a 0 ?a 7 side a inputs or 3-state outputs b 0 ?b 7 side b inputs or 3-state outputs
www.fairchildsemi.com 2 74lvxc3245 ? 8-bit dual supply configurable volt age interface transceiver with 3-state outputs truth table/s h = high voltage level l = low voltage level x = immaterial logic diagram/s inputs outputs oe t/r l l bus b data to bus a l h bus a data to bus b h x high-z state
3 www.fairchildsemi.com 74lvxc3245 ? 8-bit dual supply configurable volt age interface transceiver with 3-state outputs absolute maximum ratings (note 1) recommended operating conditions (note 2) note 1: the ?absolute maximum ratings? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the ?recommended operating conditions? table will define the conditions for actual device operation. note 2: the a port unused pins (inputs or i/os) must be held high or low. they may not float. dc electrical characteristics supply voltage (v cca , v ccb ) ? 0.5v to + 7.0v dc input voltage (v i ) @ oe , t/r ? 0.5v to v cca + 0.5v dc input/output voltage (v i/o ) @ a n ? 0.5v to v cca + 0.5v @ b n ? 0.5v to v ccb + 0.5v dc input diode current (i ik ) @ oe , t/r 20 ma dc output diode (i ok ) current 50 ma dc output source or sink current (i o ) 50 ma dc v cc or ground current per output pin (i cc or i gnd ) 50 ma and max current 200 ma storage temperature range (t stg ) ? 65 c to + 150 c dc latch-up source or sink current 300 ma supply voltage v cca 2.7v to 3.6v v ccb 3.0v to 5.5v input voltage (v i ) @ oe , t/r 0v to v cca input output voltage (v i/o ) @ a n 0v to v cca @ b n 0v to v ccb free air operating temperature (t a ) ? 40 c to + 85 c minimum input edge rate ( t/ v) 8 ns/v v in from 30% to 70% of v cc v cc @ 3.0v, 4.5v, 5.5v symbol parameter v cca v ccb t a = 25 ct a = ? 40 c to + 85 c units conditions (v) (v) typ guaranteed limits v iha minimum high a n , 2.7 3.0 2.0 2.0 v v out 0.1v level input oe 3.0 3.6 2.0 2.0 or voltage t/r 3.6 5.5 2.0 2.0 v cc ? 0.1v v ihb b n 2.7 3.0 2.0 2.0 3.0 3.6 2.0 2.0 3.6 5.5 3.85 3.85 v ila maximum low a n , 2.7 3.0 0.8 0.8 v v out 0.1v level input oe 3.0 3.6 0.8 0.8 or voltage t/r 3.6 5.5 0.8 0.8 v cc ? 0.1v v ilb b n 2.7 3.0 0.8 0.8 3.0 3.6 0.8 0.8 3.6 5.5 1.65 1.65 v oha minimum high level 3.0 3.0 2.99 2.9 2.9 v i out = ? 100 a output voltage 3.0 3.0 2.85 2.56 2.46 i oh = ? 12 ma 3.0 3.0 2.65 2.35 2.25 i oh = ? 24 ma 2.7 3.0 2.5 2.3 2.2 i oh = ? 12 ma 2.7 4.5 2.3 2.1 2.0 i oh = ? 24 ma v ohb 3.0 3.0 2.99 2.9 2.9 v i out = ? 100 a 3.0 3.0 2.85 2.56 2.46 i oh = ? 12 ma 3.0 3.0 2.65 2.35 2.25 i oh = ? 24 ma 3.0 4.5 4.25 3.86 3.76 i oh = ? 24 ma v ola maximum low level 3.0 3.0 0.002 0.1 0.1 v i out = 100 a output voltage 3.0 3.0 0.21 0.36 0.44 i ol = 24 ma 2.7 3.0 0.11 0.36 0.44 i ol = 12 ma 2.7 4.5 0.22 0.42 0.5 i ol = 24 ma v olb 3.0 3.0 0.002 0.1 0.1 v i out = 100 a 3.0 3.0 0.21 0.36 0.44 i ol = 24 ma 3.0 4.5 0.18 0.36 0.44 i ol = 24 ma i in maximum input 3.6 3.6 0.1 1.0 a v i = v cca , gnd leakage current @ 3.6 5.5 0.1 1.0 oe , t/r
www.fairchildsemi.com 4 74lvxc3245 dc electrical characteristics (continued) note 3: worst case package. note 4: max number of outputs defined as (n). data inputs are driven 0v to v cc level; one output at gnd. note 5: max number of data inputs (n) switching. (n ? 1) inputs switching 0v to v cc level. input-under-test switching: v cc level to threshold (v ihd ), 0v to threshold (v ild ), f = 1 mhz. symbol parameter v cca v ccb t a = 25 ct a = ? 40 c to + 85 c units conditions (v) (v) typ guaranteed limits i oza maximum 3-state 3.6 3.6 0.5 5.0 a v i = v il , v ih , output leakage 3.6 5.5 0.5 5.0 oe = v cca @ a n v o = v cca , gnd i ozb maximum 3-state 3.6 3.6 0.5 5.0 a v i = v il , v ih , output leakage 3.6 5.5 0.5 5.0 oe = v cca @ b n v o = v ccb , gnd ? i cc maximum b n 3.6 5.5 1.0 1.35 1.5 ma v i = v ccb ? 2.1v i cc /input all inputs 3.6 3.6 0.35 0.5 v i = v cc ? 0.6v i cca1 quiescent v cca a n = v cca or gnd supply current 3.6 open 5 50 ab n = open, oe = v cca , as b port floats t/r = v cca , v ccb = open i cca2 quiescent v cca 3.6 3.6 5 50 a a n = v cca or gnd, supply current 3.6 5.5 5 50 b n = v ccb or gnd, oe = gnd, t/r = gnd i ccb quiescent v ccb 3.6 3.6 5 50 a a n = v cca or gnd, supply current 3.6 5.5 8 80 b n = v ccb or gnd, oe = gnd, t/r = v cca v olpa quiet output 3.3 3.3 0.8 v (note 3)(note 4) maximum dynamic 3.3 5.0 0.8 v olpb v ol 3.3 3.3 0.8 v (note 3)(note 4) 3.3 5.0 1.5 v olva quiet output 3.3 3.3 ? 0.8 v (note 3)(note 4) minimum dynamic 3.3 5.0 ? 0.8 v olvb v ol 3.3 3.3 ? 0.8 v (note 3)(note 4) 3.3 5.0 ? 1.2 v ihda minimum high 3.3 3.3 2.0 v (note 3)(note 5) level dynamic 3.3 5.0 2.0 v ihdb input voltage 3.3 3.3 2.0 v (note 3)(note 5) 3.3 5.0 3.5 v ilda maximum low 3.3 3.3 0.8 v (note 3)(note 5) level dynamic 3.3 5.0 0.8 v ildb input voltage 3.3 3.3 0.8 v (note 3)(note 5) 3.3 5.0 1.5
5 www.fairchildsemi.com 74lvxc3245 ac electrical characteristics note 6: typical values at v cca = 3.3v, v ccb = 5.0v @ 25 c. note 7: typical values at v cca = 3.3v, v ccb = 3.3v @ 25 c. note 8: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). parameter guaranteed by design. capacitance note 9: c pd is measured at 10 mhz. symbol parameter t a = + 25 ct a = ? 40 c to + 85 ct a = + 25 ct a = ? 40 c to + 85 c units c l = 50 pf c l = 50 pf c l = 50 pf c l = 50 pf v cca = 2.7v?3.6v v cca = 2.7v?3.6v v cca = 2.7v?3.6v v cca = 2.7v?3.6v v ccb = 4.5v?5.5v v ccb = 4.5v?5.5v v ccb = 3.0v?3.6v v ccb = 3.0v?3.6v min typ max min max min typ max min max (note 6) (note 7) t phl propagation delay 1.0 4.8 8.0 1.0 8.5 1.0 5.5 8.5 1.0 9.0 ns t plh a to b 1.0 3.9 6.5 1.0 7.0 1.0 5.2 8.0 1.0 8.5 t phl propagation delay 1.0 3.8 6.5 1.0 7.0 1.0 4.4 7.0 1.0 7.5 ns t plh b to a 1.0 4.3 7.5 1.0 8.0 1.0 5.1 7.5 1.0 8.0 t pzl output enable time 1.0 4.7 8.0 1.0 8.5 1.0 6.0 9.0 1.0 9.5 ns t pzh oe to b 1.0 4.8 8.5 1.0 9.0 1.0 6.1 9.5 1.0 10.0 t pzl output enable time 1.0 5.9 9.5 1.0 10.0 1.0 6.4 10.0 1.0 10.5 ns t pzh oe to a 1.0 5.4 9.0 1.0 9.5 1.0 5.8 9.0 1.0 9.5 t phz output disable time 1.0 4.0 8.0 1.0 8.5 1.0 6.3 9.5 1.0 10.0 ns t plz oe to b 1.0 3.8 7.5 1.0 8.0 1.0 4.5 8.0 1.0 8.5 t phz output disable time 1.0 4.6 9.5 1.0 10.0 1.0 5.2 9.5 1.0 10.0 ns t plz oe to a 1.0 3.1 6.5 1.0 7.0 1.0 3.4 6.5 1.0 7.0 t oshl output to output t oslh skew (note 8) 1.0 1.5 1.5 1.0 1.5 1.5 ns data to output symbol parameter typ units conditions c in input capacitance 4.5 pf v cc = open c i/o input/output capacitance 10 pf v cca = 3.3v v ccb = 5.0v c pd power dissipation a b50pfv ccb = 5.0v capacitance (note 9) b a40pfv cca = 3.3v
www.fairchildsemi.com 6 74lvxc3245 power up considerations to insure the system does not experience unnecessary i cc current draw, bus contention, or oscillations during power up, the following guidelines should be adhered to (refer to table 1): power up the control side of the device first. this is the v cca side. oe should ramp with or ahead of v cca . this will help guard against bus contention. the transmit/receive control pin (t/r ) should ramp with v cca , this will ensure that the a port data pins are con- figured as inputs. with v cca receiving power first, the a i/o port should be configured as inputs to help guard against bus contention and oscillations. a side data inputs should be driven to a valid logic level. this will prevent excessive current draw. the above steps will ensure that no bus contention or oscil- lations, and therefore no excessive current draw occurs during the power up cycling of these devices. these steps will help prevent possible damage to the translator devices and potential damage to other system components. table 1. low voltage translator power up sequencing table please reference application note an-5001 for more detailed information on using fairchild ? s lvx low voltage dual supply cmos translating transceivers. configurable i/o application for pcmcia cards block diagram the lvxc3245 is a 24-pin dual supply device well suited for pcmcia configurable i/o applications. ideal for low power notebook designs, the lvxc3245 consumes less than 1 mw of quiescent power in all modes of operation. the lvxc3245 meets all pcmcia i/o voltage require- ments at 5v and 3.3v operation. by tying v ccb of the lvxc3245 to the card voltage supply, the pcmcia card will always experience rail to rail output swings, maximizing the reliability of the interface. the v cca pin on the lvxc3245 must always be tied to a 3v power supply. this voltage connection provides internal references needed to account for variations in v ccb . when connected as in the figure above, the lvxc3245 meets all the voltage and current requirements of the isa bus stan- dard (ieee p996). device type v cca v ccb t/r oe a side i/o b side i/o floatable pin allowed 74lvxc3245 3v 3v to 5.5v ramp ramp logic outputs yes, v ccb and b (power up 1st) configurable with v cca with v cca 0v or v cca i/o ? s w/ oe high
7 www.fairchildsemi.com 74lvxc3245 physical dimensions inches (millimeters) unless otherwise noted 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide package number m24b 24-lead quarter size outline package (qsop), jedec mo-137, 0.150" wide package number mqa24
www.fairchildsemi.com 8 74lvxc3245 8-bit dual supply configurable voltage interface transceiver with 3-state outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 24-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc24 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
9 www.fairchildsemi.com 74lvxc3245 ? 8-bit dual supply configurable volt age interface transceiver with 3-state outputs
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